Due to the constant push for smaller and smaller products, it has become common for integrated circuits (ICs) once contained on two or more individual semiconductor die or chips to be combined into a single, larger IC device. For example, traditional microprocessor circuits are being combined on a single chip with digital signal process circuits. These combined ICs have the advantage of better reliability due to fewer total external connections, but have higher input/output (I/O) counts than many of the individual ICs. Often, these combined devices have I/Os in the 200+ range. Additionally, new ICs are being designed "from the ground up" with many advanced features which also result in 200+ I/Os. Thus, high I/O counts are becoming more and more commonplace.
Over Molded Pad Array Carrier or OMPAC is one successful method for containing relatively large I/O count into a small footprint at low cost. The OMPAC package (a type of ball grid array or BGA package) consists of a printed circuit board (PCB) or other insulating material substrate having a plurality of conductive traces on both the top and bottom surfaces, vias connecting the top traces to the bottom traces, and solder pads at ends of the bottom traces. The traces, vias, and pads, are typically formed of copper and are subsequently plated with nickel and gold. A semiconductor die is attached to the top of the substrate, and wires are used to electrically couple the die to the top set of traces. An organic encapsulation is applied over the die, wires and portions of the top of the substrate. A mass of solder in the form of spheres, paste, or plating is then applied to the solder pads on the bottom of the package. Since OMPAC packages have an array of solder pads covering most of the package bottom, the package is typically much smaller than corresponding peripherally leaded packages. An array takes advantage of the entire area of the package, whereas peripherally leaded packages can only take advantage of the outer perimeter of the package.
Due to the basic nature of the package components, OMPAC is considered a low cost package. The most expensive individual cost component is the substrate. The cost of a single layer, double sided substrate is significantly lower than that of a multilayer substrate and is therefore preferred for OMPAC applications. One of the limitations of single layer substrates is the restriction in routing electrical connections from the vias to an external plating bus formed at the periphery of the package. Electrical connections to the plating bus are required for electrolytic plating of nickel and gold onto those portions of the copper laminate which will be used for subsequent electrical bonding (i.e. die bonding, wire bonding, and solder ball reflow) or for electrical probing and testing. The nickel and gold plating layers protect the copper from oxidation, resulting in a surface which is easier to bond and probe. In order to accomplish electrolytic plating, all conductive parts which are to be plated are electrically short-circuited so that necessary current applied during the electrolytic process easily passes through all members to be plated. This is typically accomplished by routing all members to an external plating bus. The bus must eventually be removed to create electrical isolation between the various conductive features.
To achieve a higher I/O count without increasing package size and without moving to a multiple layer substrate, the routing density (i.e. number of traces per unit area) on the outer surfaces must be increased. The routing density of a substrate used in OMPAC packages is dictated by the size of the via holes, the size of the annular rings surrounding each via hole, the solder pad diameter, the minimum copper trace width and the minimum gap between copper traces. Depending on the capabilities of the substrate manufacturer and on the I/O count of the package, the external plating connections also often directly limit the number of discrete I/O connections possible for single layer substrate packages. In other words, the need to connect all traces to an external, peripheral plating bus often restricts the routing density for a given size substrate.
In the case of a typical OMPAC substrate, (assuming 1.5 mm solder pad pitch, 0.25 mm via diameter, 0.50 mm annular via ring diameter, 0.89 mm solder pad diameter, 0.1 mm copper trace width and 0.1 mm gap between copper traces), it is possible to have up to 3 traces between vias on the top surface of the package, and to have up to 2 traces between solder pads on the bottom surface. These traces can be used to either route from wire bond fingers to vias (where wire bond fingers are pads at the ends of top surface traces which surround the die and which receive the bonding wires), or from vias to the external plating bus. These figures put a lower limit on the size of a particular substrate for a given number of I/Os. In order to achieve additional routing, and thus a higher I/O count, with the current single layer OMPAC substrates, the via and solder pad pitches would have to be increased to allow more traces to fit between pads and vias, or the via and solder pad diameters would have to be decreased. Increasing the solder pad and via pitches undesirably increases the size of the substrate and size of the final package, whereas decreasing solder pad and via diameters would undesirably increase the cost to manufacture the substrate and reduce the solder joint strength due to the smaller solder pads. Accordingly, it would be desirable to eliminate the need to route traces to external plating buses. This would reduce the number of traces that need to be routed between vias and between solder pads, thereby keeping substrate size to a minimum while increasing routing density.
One known solution to the routing problem imposed by the need to route traces to an external plating bus is the use of so-called "electroless" plating processes. External plating connections would not be required if the substrates were nickel and gold plated using electroless plating techniques since electroless plating does not require all conductive elements to be short-circuited together. However, electroless plating is inherently thinner and more porous than electrolytic plating which makes it marginal at preventing oxidation of the underlying copper. This in turn makes it more difficult to achieve good, reliable bonding onto the plated surfaces. Consequently, the use of electroless gold plating is limited to special cases where the time and temperature exposures are short and low enough that the resulting oxidation does not impede the creation of reliable bonds.
Therefore, an alternative to the existing external peripheral plating bus used in OMPAC semiconductor devices, and similar devices having wired substrates, would be desirable. Moreover, such an alternative should improve the existing plating process by allowing more traces and vias to be formed in a given area of the substrate than presently possible.